MIPS SysProbe SP55E High Performance Trace Probe for MIPS 32-bit and 64-bit Cores

sp55e_angle_front

 
 

MIPS SysProbe SP55E, the newest probe technology from Imagination Technologies, supports all MIPS cores including the latest Warrior class.

By taking advantage of advanced on-chip debug and optional trace features in Imagination’s IP cores, the SysProbe SP55E allows fast and efficient debug without requiring an intrusive software monitor or additional target I/O resources.

The SysProbe SP55E provides a full debugging feature set including software and hardware breakpoints, hardware triggers, reset control, power monitoring, code profiling and much more. These features provide the tools that meet the needs of today’s cutting edge development teams for first silicon bring-up, hardware and software development, debug and verification activities.

The SysProbe SP55E typically connects to the target system using a 14-pin debug connector but it has the flexibility to adapt to different debug connectors and protocols. The debugging software is cross-platform and runs on Windows®, Linux®, or OS X® computers, communicating via USB 2.0 or up to 1Gb Ethernet.

At the heart of the probe is a powerful MIPS processor running Linux to give the highest debug performance.

Designed for a multi-cluster multi-core future

Today’s ever more complex chips present new debug challenges with System-on-Chip (SoC) systems comprising multiple IP designs containing many cores and multi-threading capabilities. The SysProbe SP55E supports the latest MIPS On-Chip Instrumentation (OCI) debug architecture and offers simultaneous debug of heterogeneous designs (CPU, RPU and GPU) within a single SoC. To simplify software setup, the SysProbe SP55E can automatically detect which cores are present and the debug bus topology in the SoC.

Hardware/software breakpoints and triggering

Software breakpoints can be set anywhere in RAM using the core SDBBP instruction. MIPS cores can also include a number of hardware breakpoints which are configured in the core design. A typically-configured core might have four instruction breakpoints recognizing an executed virtual address, and two data breakpoints recognizing data loads and stores to virtual addresses with maskable data values. MIPS M-class cores support Complex Break and Trigger (CBT) hardware features: pass counters, tuples, primed breakpoints, and qualified breakpoints. Hardware breakpoints can be qualified with Address Space Identifier (ASID) to break only when a particular task is active.

Flexible trace options

MIPS cores support on-chip and off-chip trace depending on the system options configured by the chip designer. The SysProbe SP55E hardware and software supports trace execution history captured in an on-chip trace buffer and accessed over the Test Access Port (TAP). Trace can selectively include load/store address, load/store data, and processor mode and exception information. The trace output can be filtered to focus on specific types of information to most effectively solve a debug problem. Two other SysProbes from Imagination, the SP55ET and the SP58ET, support off-chip iFlowtrace and off-chip PDtrace (program and data trace).

Features

  • Support for all MIPS cores and other Imagination IP including:
    • Warrior cores including P-class (P56xx), M-class (M51xx) and I-class (I64xx) cores.
    • proAptiv, interAptiv, and microAptiv cores.
    • MIPS32 classic cores including: M4K, 4K, 4KE, 24K, 24KE, 34K,74K,1004K and 1074K.
    • Ensigma RPU Series 3, 4 and 5 MCP Cores.
    • Embedded Controller (Meta) within Graphics and Video IP cores.
  • Uses a high performance MIPS processor running Linux for higher performance and lower communications overhead.
  • Simultaneous debug of multi-core, multi-threaded heterogeneous designs.
  • Auto-detection of cores and bus topology.
  • Supports on-chip trace capture.
  • PC execution trace, load/store address, and load/store data trace supported if configured in the core.
  • Trace can be gated on/off by hardware breakpoint triggers.
  • Unlimited software breakpoints.
  • Code and data hardware breakpoints supported.
  • Single step by assembly or C/C++ source line.
  • Read/write all CPU, CP0 and peripheral registers.
  • Program counter (PC) sampling for zero-overhead code profiling (when supported by the core).
  • Go, halt, single-step processor run control.
  • Low-level access to JTAG functions for silicon verification.
  • Comes with Codescape Console, a Python based command-line debugger. Easy to create scripts, utilities, regression tests etc.
  • Supports filtered trace to capture only function call-returns or hardware execution or data triggers in the trace, and optionally up to four performance counters (when supported by the core).
  • Supported by Codescape MIPS SDK Professional.

Codescape_Development_system

Codescape Console command line interface

Imagination supplies an advanced scripting and command-line console, Codescape Console, that enables direct access to the SysProbe SP55E from the host PC without using the Codescape Debugger user interface. This provides an ultra-low-level, non-intrusive, scripting layer that is ideal for target bring-up. It allows performance of tasks such as reading and writing memory and registers, or manually controlling JTAG signals, with a predictable impact on the target. Codescape Console is based on the popular Python programming language and is fully configurable and expandable. Chip and hardware designers can create powerful routines for verifying their SoC designs for regression and hardware-level verification. End users can write loadable functions to automate initialization sequences (e.g. for peripheral setup), before boot code has been developed.

More information

Source-level debug

For source-level debug with a rich GUI, the SysProbe SP55E is tightly coupled with Codescape Debugger. Codescape Debugger is included with Codescape SDK Professional, Imagination’s bespoke software development and debug environment. Codescape Debugger provides a number of viewing regions and options to organize display of the code execution and target system information. Regions include Source code, Disassembly, Call Stack, Local and Watch variables, CPU and Peripheral registers, Memory, Breakpoints, Hardware triggers, Trace, Instruction and Data Caches, and console I/O, among others. The windowed environment is designed to maximize developer productivity for faster results and ease of use. Codescape Debugger also includes advanced features such as RTOS awareness and Linux task debugging.

Host Requirement:

X86 PC with minimum 8 GB memory
Windows® 7 or later (64-bit)
Red Hat RHEL 6 (64-bit)
Mac® OS X®