I am trying to understand how those two instructions work. I read the MIPS manual and it says (BCzT), “Compute a branch target address by adding address of instruction in the 16-bit offset (shifted left two bits and signextended to 32-bits). Branch to the target address (with a delay of one instruction) if co-processor z’s condition line is true.” So I understand how the address is calculated but the part I don’t understand is the, ” if co-processor z’s condition line is true”, part. What condition line is it talking about? Which register? Is it talking about the 4 MSBs of the status register in COP0? Thanks!
Oh thanks. That clears up things. I am working on Playstation 1 system and it lacks FP unit so any coprocessor 1 instructions won’t get executed. Coprocessor 2 is GPU so maybe it uses those instructions.
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