March 28, 2017 at 11:28 pm #55534
Over the last few evenings I’ve tried a few different times to walk through the MIPSfpga SoC guides to the point that I should have effectively replicated the design in Vivado 2016.2. I allowed block automation to run for the MIG 7-series, which resulted in an error about “board_if”. After a short search, it was stated on a Digilent forum that the error can be ignored since I’m using the Nexys4 DDR board definition file in my project.
When I try to validate the resulting design, I end up with an error repeated for every M_AXI to S_AXI connection between an interconnect and a given peripheral (other than the MIG) that states:
Bus Interface property FREQ_HZ does not match between [the S_AXI] and [the M_AXI at the interconnect].
Most of the solution’s I’ve found online state that the issue was related to not having a clock generator (and installing one fixes the issue). The error statement above has details stating that the slave side is at 100 MHz and the master is at 10 MHz. My clock generator seems to be configured identically to the one in the 2014.4 version of the project (I opened it in 2014.4 and used it as a reference while I worked), I’m not seeing how this could be the case.
Has anyone else seen this (even in relation to another problem)?March 29, 2017 at 5:17 am #55535
IIRC, I have seen this before. The exact solution escapes my memory.
I think when the Axi interconnect is created, it defaults to 100MHz for whatever reason.
And we connect the clock afterwards, which causes this. Ideally, it should derive the clock for the block from the source clock.
The work around is when to click the axi interconnect block, check the properties. There is a freq_hz property of the block (or the clock line). The clock parameter needs to be set to 50MHz. Or whatever your system clock is.
And I think I also tried simply deleting the axi interconnect block and putting it again.
ZubairLKMarch 29, 2017 at 11:32 pm #55536
What I was seeing is that the AHBLite to AXI bridge master would default to 100 MHz and the interconnect S00 and all masters would default to 10 MHz. I went every which way I could think of with connecting things up, but it always ended up this way (even swapping the order in which I connected things).
Last night on a whim I decided to edit my MIPSfpga IP core back in the IP packager. In the original design guide, it says to infer the AHBlite interface, but it never talks about the clock. I figured, why not try the clock?
I selected HCLK, right-clicked, and selected Auto Infer Single Bit Interface -> Clock. I was then greeted with a Vivado warning that FREQ_HZ was not set. Bingo.
Right click HCLK again, and select Edit Interface. Then pick Parameters and add FREQ_HZ for whatever value, 50 MHz is more likely correct given the clock generator configuration, so I set it to 50000000. After repackaging and closing the project, I let Vivado upgrade and re-attempt generating output products. No more FREQ_HZ issues with the interconnect, but I did get issues about async reset warnings.
These async reset warnings about HRESETn and the interconnect can be fixed similarly by marking HRESETn as a reset and then for HCLK, add another attribute pointed back at HRESETn: ASSOCIATED_RESET.
I’m now left with it complaining about the async reset between the MIG and HRESETn.
Thanks, and I hope this helps. 🙂May 10, 2017 at 2:31 pm #55813
Hi Thomas. I’m about to migrate to a newer version of Vivado myself and was wondering if the warnings about async reset between MIG and HRESETn is still an issue.
Also, in your other post you mentioned you updated the MIPSfpga RTL. Did you use MIPSfpga-plus?
Looking forward to your response and thanks for all your contributions so far.