Codescape MIPS SDK / proSDK cycle accurate instruction set simulator/emulator

This topic contains 6 replies, has 2 voices, and was last updated by  Avantika 2 years, 8 months ago.

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  • #31971

    Avantika
    Member

    I need to measure number of cycles (including all CPU stalls) which code will take at MIPS CPU.
    Unfortunately it was not mentioned in Codescape MIPS SDK / proSDK products description, do they provide cycle accurate instruction set simulation/emulation (without any real HW available)?
    Which of Codescape MIPS SDK / proSDK products and which included simulator/emulator could be used for this purpose?

    #39470

    Sean
    Moderator

    The Codescape MIPS Essentials SDK provides QEMU emulator giving an instruction accurate simulator. You can use the count registers in order to count the number of cycles (i.e. sample at beginning/end and take the difference).

    The GCC toolchain provided has a number of MIPS specific headers to assist you in accessing this register. include mips/cpu.h and use the function mips_getcount()

    Please be aware that this register wraps every 0xFFFFFFFF instructions. In order to detect this wrap you would need to develop additional code to handle using interrupts.

    Hope that helps?

    Sean.

    #39471

    Avantika
    Member

    Unfortunately not.
    I have tried to use mips_getcount() to measure cycles. The problem I got that measured cycles number for several instruction gives always different results from ~10000 till ~30000 cycles. Therefore I think it is incorrect.

    Could you please clarify which target should be used for QEMU to have instruction accurate simulator?

    #39472

    Sean
    Moderator

    Ok, thanks for letting me know. I’ll be honest – I’ve never actually used the CP0.count registers on QEMU, only on real hardware.

    In QEMU the calculation is based on internal QEMU timers. It’s not immediately clear why returned values differ so much.

    What you can do however is to enable virtual instruction counter on QEMU to get reproducible results, for example “-icount auto”:

    -icount [shift=N|auto][,align=on|off]
    enable virtual instruction counter with 2^N clock ticks per
    instruction and enable aligning the host and virtual clocks

    I’m afraid I’m not able to test this at the moment – would you be give it a go and let me know if this gives you the results you need?

    Sean.

    #39473

    Avantika
    Member

    Thank you for the hint!
    -icount option allow to fix returned cycles count during several run. Unfortunately returned value could be used only as not accurate number of executed instruction. And it is definitely not cycle accurate instruction counter output. Therefore I would like to return to my first question:
    Which of Codescape MIPS SDK / proSDK products and which included simulator/emulator could be used for cycle accurate measurements?

    #39474

    Sean
    Moderator

    The Codescape MIPS SDK is not intended to support the capability to provide precise H/W performance information other than via H/W emulated, FPGA or real target platforms. I am sorry for leading you in the wrong direction if QEMU is not capable of providing the measurements you require.

    Is there a reason you cannot use hardware to achieve this measurement? There are a number of 24K based platforms available fairly cheaply, Ubiquiti RouterStation for example.

    Sean.

    #39475

    Avantika
    Member

    Thanks a lot for your answer. In this case we will use HW for our measurements.

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