- February 16, 2015 at 10:17 am #31970
If I understand it correctly the mfc0 instruction is only available in kernel mode and the rdhwr (which I’ve used on other mips to get this info) is not available for mips2.
Is there an easy way to get a cycle count (or another “reliable” measurement for performance) without writing a kernel module with syscalls?February 16, 2015 at 3:39 pm #39469
First of all I’d like to point out that whilst the debian binaries shipped on the CI20 by default are built for the mips2 ISA (since that’s what the debian project choose to target), the XBurst cores in the jz4780 SoC used on the CI20 actually implement the mips32r2 ISA. Although they both end with “2”, the latter is somewhat newer & does include support for the rdhwr instruction so that instruction in itself should be safe to execute. Additionally, the kernel does implement support for emulating the rdhwr instruction on older systems which don’t provide it anyway (http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/mips/kernel/traps.c#n608).
However, the problem you’re likely to face here is that the XBurst CPU cores don’t actually implement the coprocessor 0 count & compare registers (aka r4k timer in kernel nomenclature). Which unfortunately means right now the answer is likely “no”… It should be possible to have the kernel disable the native rdhwr instruction for the count case though, and emulate it by returning something based upon a timer from the jz4780 timer/counter unit.