Does MIPSfpga support multicore? If you don't need cache-coherence, yes


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    Several professors asked me whether MIPSfpga support building multi-core systems.

    The answer depends on whether you talking about multi-core systems with cache coherence or without cache coherence.

    If “with cache coherence”:

    MIPSfpga is not suitable for cache coherence protocols (MESI and similar). Some very advanced students or researchers can implement MESI protocol in MIPSfpga by replacing MIPSfpga modules for caches and writing their own coherence manager block. However the resulting implementation is not likely to be practical in terms of performance improvement. Multi-core with cache coherence becomes practical only for MIPS mid-range (MIPS interAptiv, MIPS I6400) or high-end (MIPS P5600, MIPS P6600) cores which are available only for commercial licensing.

    If “without cache coherence”:

    MIPSfpga can be used for specialized multicore systems where each core has its own mostly separate memory space and the cores exchange information with each other infrequently, via some logic (like FIFOs) connected to memory-mapped registers in uncached address space. This is an important area for academic creativity. However keep in mind that such way of using MIPSfpga is practical only for _some_ applications like parallel internet packet processing, but is not practical for general-purpose computing.

    Same thing is applicable to MIPSfpga commercial relatives – MIPS microAptiv UP and MIPS M5150.

    If you don’t know the meaning of “cache coherence” and “MESI”, you can start from Wikipedia:

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