- May 18, 2017 at 4:46 am #55974May 18, 2017 at 10:29 am #55977
If I understand correctly, you are asking if the caches are mapped to the address space, am I right?
The answer is no, they do not have their own addresses in the memory map. Instruction and data caches store local copies of some of the contents of main memory so that the access time by the CPU to that information is faster. Instruction and data caches are internal to the CPU pipe and not visible* from the outside, in particular not from the memory map or address space.
I hope this solved your question,
* You can actually interact directly with the cache through cacheops and sync instructions, but that’s a different topic of discussion 🙂May 18, 2017 at 11:02 am #55978
The answer to this question varies depending on what angle you are looking from.
From a HW perspective, the physical address space is not taken up by the caches.
From a SW perspective, the answer is slightly tricky. The microAptiv has a memory management unit.
From the perspective of the MIPS core, the physical address space is mapped to a virtual address space.
For further detail, check the microAptiv Software User Manual in the documentation. There is a section on Memory Management Unit. Another helpful resource is http://www.johnloomis.org/microchip/pic32/memory/memory.html
ZubairLKMay 18, 2017 at 12:26 pm #55979
Thanks for your replies
From the figure you can see that cache is mapped to the physical address from 0x0 to 0x3fffcMay 18, 2017 at 2:55 pm #55980
The cache will contain instructions and data that is stored in addresses 0x0 to 0x3fffc, but that is different from saying that it is mapped to those physical addresses. At least, in the way usually memory mapping is understood.
E.May 21, 2017 at 3:25 am #55992
You mean that instruction or data cache only will cache instruction or data form 0x0 to 0x3ffffc,but cache has no its own address,no use the physical address space