FAQ: Find the right Vivado License for MIPSfpga

This topic contains 3 replies, has 3 voices, and was last updated by  Nicholas 1 year, 6 months ago.

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  • #53130

    Laurence
    Admin

    MIPSfgpa
    When Installing Vivado for the Nexys4 DDR FPGA Board (Appendix B of Getting Started Guide), Step 3 recommends to select a “Vivado WebPACK License” (Getting Started Guide – Figure 107). However, Xilinx has recently included the High-Level Synthesis (HLS) for free in the WebPACK and the Debug Tools. Thus, the new Activation Based License “Vivado Design Suite: HL WebPACK, Node-Locked License” can be selected instead for licensing Vivado.
    MIPSfpga SoC is currently on version 2014.4, but it will be updated by the end of 2016.

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    #53386

    Nicholas
    Member

    Laurence,

    Can you confirm that the only Vivado version that will run MIPSfpga (not just MIPSfpga SoC) is 2014.4? I have a 64 bit windows 10 system, with a Nexys 4 DDR and the Bus Blaster with the Codescape Software Development Kit.. While I can load code into the Nexys 4 system, I am not able to get it to single step and halt at break points. I have tried both 2014.4 and 2015.4. I am looking for solutions to get single step and break points working.

    Thank-you,
    Nick

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    #53389

    Enrique
    Member

    Hi Nicholas,

    The Vivado version should not affect the capacity of setting breakpoints and single stepping.

    There is one thing you have to be sure when you follow Lab02 to debug the program. All your MIPSfpga scripts and sofware sources must be in paths that do not contain spaces in them. For example, as you can see in page 10 of the MIPSfpga_Lab02_CProgramming.pdf document, the command

    loadMIPSfpga.bat C:\MIPSfpga_Fundamentals\Xilinx\Lab02_C\ReadSwitches

    is in a path without spaces. If you load a program with a path with spaces in it, say:

    loadMIPSfpga.bat C:\My Documents\MIPSfpga\Xilinx\Lab02_C\ReadSwitches

    you will be able to load the program just fine, but the gdb connection will fail.

    Please try this and let us know if it fixed the problems you are having. Otherwise, please let us know what type of errors you are having so we can try and find the appropiate solution for the failure.

    Thanks!
    Enrique.

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    #53421

    Nicholas
    Member

    Enrique,

    Thank-you for your fast reply. Unfortunately, I am following the directions in Lab02 exactly, and my directory structure is setup exactly as you have suggested (no spaces). I am going to put the output from the loadMIPSfpga.bat script after this message, and maybe it might suggest a cause. I am curious about one other point. The Nexys4_DDR board is loaded with the MIPSfpga code first, and it is connected with it’s own USB cable. I then plug in the busblaster connection, and then connect my second USB cable to the bus blaster. The instructions don’t give a diagram that show that type of connection, but the Nexys4 board has to be connected inorder to save the code.

    Is that the correct configuration? The instructions only mention connecting the BusBlaster via the USB cable.

    Here is the log from the two cmd windows:
    Open On-Chip Debugger 0.9.1-dev-microAptiv-dirty (2015-05-08-15:32)
    Licensed under GNU GPL v2
    For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
    adapter speed: 15000 kHz
    adapter_nsrst_delay: 100
    trst_and_srst separate srst_gates_jtag trst_open_drain srst_open_drain connect_d
    eassert_srst
    Change MIPS Bus Blaster Default Adapter speed
    adapter speed: 14000 kHz
    scan delay: 20000 nsec
    running in fast queued mode
    Info : clock speed 14000 kHz
    Info : JTAG tap: mAUP.cpu tap/device found: 0x00000001 (mfg: 0x000, part: 0x0000
    , ver: 0x0)
    Info : accepting ‘gdb’ connection on tcp/3333
    Warn : target not halted
    Info : JTAG tap: mAUP.cpu tap/device found: 0x00000001 (mfg: 0x000, part: 0x0000
    , ver: 0x0)
    Error: timed out while waiting for target halted
    TARGET: mAUP.cpu – Not halted
    in procedure ‘reset’
    in procedure ‘ocd_bouncer’

    in procedure ‘reset’
    Warn : target not halted
    Warn : target not halted
    Info : Halt timed out, wake up GDB.

    Second window:
    Reading symbols from FPGA_Ram.elf…done.
    0x00000000 in ?? ()
    The target is assumed to be little endian
    JTAG tap: mAUP.cpu tap/device found: 0x00000001 (mfg: 0x000, part: 0x0000, ver:
    0x0)
    timed out while waiting for target halted
    TARGET: mAUP.cpu – Not halted
    in procedure ‘reset’
    in procedure ‘ocd_bouncer’

    in procedure ‘reset’
    Loading section .exception_vector, size 0x320 lma 0x80000000
    Loading section .text, size 0x16ec lma 0x80000320
    C:\MIPSfpga_Fundamentals\Scripts\Nexys4_DDR\..\startup.txt:4: Error in sourced c
    ommand file:
    Load failed
    (gdb)

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