How EIC encoder encodes 0-63 interrupts in just 5 hardware lines, in MIPS InterAptive core ?

This topic contains 19 replies, has 4 voices, and was last updated by  Sean 4 years ago.

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  • #31425

    I am looking for the External Interrupt Controller (EIC) interrupt encoder logic, how EIC encodes 0-63 External interrupts to just 5 hardware line (per VPE’s).
    I have gone through all the document which Describes EIC mode interrupt handling but their in no information available for EIC interrupt encoder, please let me know if I am missing anything…

    #37837

    chenny
    Member

    The external interrupt controller prioritizes its interrupt requests and produces the vector number of the highest priority
    interrupt to be serviced. The vector number, called the Requested Interrupt Priority Level (RIPL), is a 6-bit
    encoded value in the range 0..63, inclusive. A value of 0 indicates that no interrupt requests are pending. The values
    1..63 represent the lowest (1) to highest (63) RIPL for the interrupt to be serviced. The interrupt controller passes this
    value on the 6 hardware interrupt line, which are treated as an encoded value in EIC interrupt mode.

    #37838

    Thanks for the reply, if the current IPL is > RIPL then only the interrupt will be serviced so every time I need to write RIPL register ?

    #37839

    What is the use of EIC mode if I am not able to select the priority by my self, for ex as 63 is the highest priority and I want to make 40th interrupt as the highest priority, Can I do that? because for ex RIPL contents is 62 hence will not receive the interrut because current IPL (40) is less then RIPL (62)….

    #37840

    chenny
    Member

    StatusIPL is interpreted as the Interrupt Priority Level (IPL) at which the processor is currently operating. When the interrupt controller requests service for an interrupt, the processor compares RIPL with StatusIPL to determine if the requested interrupt has higher priority than the current IPL. The interrupt will only be serviced if RIPL > IPL. RIPL is not a software programmable register, but StatusIPL can be modified by software.

    #37841

    chenny
    Member

    When using EIC mode, it’s assumed you already have an external interrupt controller (hardware) outside a MIPS core. The external interrupt controller, a custom design, will be the one setting the request priority.

    #37842

    QEMU for mips InterAptive is available ?

    #37843

    My question is not 100% correct, I mean to ask the is mips interaptive support is available in QEMU …

    Thanks

    #37844

    Hi, I am using MALTA-MTI InterAptive board I want to enable Interupt-EIC mode in linux, I have enable cpu_has_eic flag in cpu_features.h and also enable EIC bit in GIC_VPE_CTL_LOCAL reg. I could see the YAMON restarts by saying Unregister interrupt controller event occured”. are my steps are valid to enable EIC mode ?

    #37845

    ChrisImgtec
    Moderator

    Which version of Linux are you using? EIC works starting with 3.8.

    #37846

    oh ! Thanks for the clarification, I am using 3.4 now I will try 3.8, are my steps are correct to enable EIC mode…

    #37847

    Hi,
    Is there are any specific steps to enable EIC mode in MTI-Linux 3.8.x ?

    #37848

    ChrisImgtec
    Moderator

    I have been told “it should just work”. I also don’t see anything wrong with the steps you are taking.

    #37849

    Thanks for reply, I think my steps are not correct hence YAMON restarts by saying “Unregister interrupt controller event occured” . One more big issue is even enabling EIC I am not able to see the EIC bit enable in C0_Status register.

    #37850

    Sean
    Moderator

    Given you can’t see the EIC bit enable in C0_Status register, it would seem possible that the FPGA bitstream may not have EIC support in it.

    Please can you let me know the bitstream that you are using (send me a private message if you would prefer not to disclose publicly).

    Regards,

    Sean.

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