How to setup EBASE address for Dual Images with MMU enabled in the 0xC000 0000 area???

This topic contains 1 reply, has 2 voices, and was last updated by  ChrisImgtec 3 years, 11 months ago.

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  • #31402

    rogeryung
    Member

    1. If we load our dual images in the  0xC000 0000 segment, how should we setup the EBASE
      address at start-up??? According to the MIPS
      32 spec, the Bits 31 and 30 of EBASE register are READ-ONLY and default with
      value of 0b10. As a result, we can’t load the EBASE register with anything higher than “0xC000 000”
      because the EBASE address has to be in an unmapped segment ranging from 0x8000
      0000 to 0xBFFF FFFF. With this restriction, how can we support dual images with
      our exception vectors in two different code blocks?

    Spec snippet from MIPS32:

    “Bits 31..30 of the EBase register
    are fixed with the value 0b10,and the addition of the base address and the
    exception offset is done inhibiting a carry between bit 29 and bit 30 of the
    final exception address. The combination of these two restrictions forces the
    final exception address to be in the kseg0 or kseg1 unmapped virtual address
    segments. For cache error exceptions, bit 29 is forced to a 1 in the ultimate
    exception base address so that this exception always runs in the kseg1
    unmapped, uncached virtual address segment.”

    #37794

    ChrisImgtec
    Moderator

    You can’t you can only use the KSEG1/KSEG0 address. In some newer MIPS implementations that conform to MIPS32 release 3 can use extended virtual addressing and segmentation control this is no longer a restriction and bits 30,31 can be changed.

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