MIPSfpga+: Connecting parts and running synthesis for Altera Terasic DE0-CV

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    Yuri
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    An appendix to the main article MIPSfpga+ allows loading programs via UART and has switchable clock

    Copy at http://github.com/MIPSfpga/mipsfpga-plus/wiki

    Information about GPIO pin assignment:

    How to synthesize mipsfpga-plus for Terasic DE0-CV board:

    1. Unzip MIPSfpga to C:\MIPSfpga
    2. Get mipsfpgfa-plus into C:\github\mipsfpga-plus
    3. cd C:\github\mipsfpga-plus\boards\de0_cv
    4. make_project.bat
    5. Run Altera Quartus II
    6. Open project C:\github\mipsfpga-plus\boards\de0_cv\project\de0_cv.qpf
    7. Analyze/Synthesize/Place&Route/Assemble
    8. Open Device / Hardware Setup / ByteBlaster / Set file / ouput_files / de0_cv.sof / Start

    How to load a software example into mipsfpga-plus using BusBlaster and OpenOCD:

    cd C:\github\mipsfpga-plus\programs\00_counter
    02_compile_and_link.bat
    10_upload_to_altera_board_using_bus_blaster.bat
    

    How to load a software example into mipsfpga-plus using USB-to-UART-based serial loader:

    cd C:\github\mipsfpga-plus\programs\00_counter
    02_compile_and_link.bat
    08_generate_motorola_s_record_file.bat
    11_check_which_com_port_is_used.bat
    

    Modify 12_upload_to_the_board_using_uart.bat.

    12_upload_to_the_board_using_uart.bat
    
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