modifying exception_entry.S for EIC + GPIO interrupt handling

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This topic contains 5 replies, has 3 voices, and was last updated by  Ken 3 days, 18 hours ago.

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  • #56670

    Ken
    Member

    Hi, I’m trying to use a button(BTNC) as an interrupt source to drive the LED action. When I download the program to the board via bus blaster, it shows:
    OpenOCD

    gdb

    Problem: I don’t know how to fix this error. And I want to know whether the exception_entry.S file is correct or not.

    Here’re some details:
    hw: Nexys4 FPGA board, BusBlaster
    sw: Vivado2014.4
    My block design: see the PDF(*.*)

    design_intC_led

    My C program files:

    LED_irq

    I am looking forward to your suggestions.

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    #56678

    Daniel
    Member

    Hi Ken,
    A simpler option than using an External Interrupt Controller as you are trying to do would be to use the default interrupt mode. Lab 10 in the MIPSfpga-Labs package does so (I’m attaching a reduced version of that lab, which corresponds to one of the activities that we did at FPL Workshop last september. It includes the guidelines, bitstream, and C program). Please, take a look at it, and let us know if this is enough for your goals or you still need to use an EIC, in which case we can try to help you further.
    Best regards
    Dani

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    #56680

    Bruce
    Member

    The problem with the OpenOCD startup is probably the scan_delay setting. The smaller values provide a speed optimization to the connection between the PC and Bus Blaster but can sometimes be unreliable. Change the value set in the OpenOCD config file xilinx_nexys4_mips.cfg (at the bottom) in the path ..\scripts\target to a value of 2000000 (i.e. 2 million) or greater. That changes the mode to non-optimized and hopefully will solve the connection problem.

    — Bruce Ableidinger
    MIPS LLC

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    #56683

    Ken
    Member

    Hi Daniel,
    Thanks for your suggestion.
    We are trying to teach the students about the knowledge of interfaces, and we found it much easier to use those block IPs provided by Vivado and help to understand the concept of interface. Besides, we can only get access to the those resources provided here: https://community.imgtec.com/university/resources/ (already have Lab01~Lab09, Fundamentals-v.1.2) If time is permitted, I’d like to try the way you recommended. BTW, I want to know where I can get the MIPSfpga-Labs package you have mentioned.
    Best regards
    Ken

    • This reply was modified 3 days, 18 hours ago by  Ken.
    #56684

    Daniel
    Member

    Hi Ken,
    In the web page you are referring you can find the package, specifically under: Teaching&Training – MIPSfpga – English – MIPSfpga Labs v2.0. Given your teaching goals, maybe you will also find useful the third package of MIPSfpga, called MIPSfpga SoC.
    The paper entitled “MIPSfpga: using a commercial MIPS soft-core in computer architecture education” describes in detail the 3 packages of MIPSfpga: (1) MIPSfpga GSG; (2) MIPSfpga Labs; and (3) MIPSfpga SoC. If you cannot access the paper, please give me your e-mail and I’ll send it to you.
    Please let me know if you need more help.
    Best regards

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    #56686

    Ken
    Member

    Daniel,
    Thanks a lot. I have found the paper and it looks great. Last time I have got Fundamentals v.1.2 which only includes Lab01~Lab09 from this website. As a green hand studying at MIPSfpga, it really helps.
    Sincerely

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