- October 12, 2017 at 8:13 am #56670
Problem: I don’t know how to fix this error. And I want to know whether the exception_entry.S file is correct or not.
Here’re some details:
hw: Nexys4 FPGA board, BusBlaster
My block design: see the PDF(*.*)
My C program files:
I am looking forward to your suggestions.
Attachments:You must be logged in to view attached files.October 13, 2017 at 10:59 am #56678
A simpler option than using an External Interrupt Controller as you are trying to do would be to use the default interrupt mode. Lab 10 in the MIPSfpga-Labs package does so (I’m attaching a reduced version of that lab, which corresponds to one of the activities that we did at FPL Workshop last september. It includes the guidelines, bitstream, and C program). Please, take a look at it, and let us know if this is enough for your goals or you still need to use an EIC, in which case we can try to help you further.
Attachments:You must be logged in to view attached files.October 13, 2017 at 7:54 pm #56680
The problem with the OpenOCD startup is probably the scan_delay setting. The smaller values provide a speed optimization to the connection between the PC and Bus Blaster but can sometimes be unreliable. Change the value set in the OpenOCD config file xilinx_nexys4_mips.cfg (at the bottom) in the path ..\scripts\target to a value of 2000000 (i.e. 2 million) or greater. That changes the mode to non-optimized and hopefully will solve the connection problem.
— Bruce Ableidinger
MIPS LLCOctober 14, 2017 at 10:15 am #56683
Thanks for your suggestion.
We are trying to teach the students about the knowledge of interfaces, and we found it much easier to use those block IPs provided by Vivado and help to understand the concept of interface. Besides, we can only get access to the those resources provided here: https://community.imgtec.com/university/resources/ (already have Lab01~Lab09, Fundamentals-v.1.2) If time is permitted, I’d like to try the way you recommended. BTW, I want to know where I can get the MIPSfpga-Labs package you have mentioned.
October 14, 2017 at 11:57 am #56684
- This reply was modified 3 days, 18 hours ago by Ken.
In the web page you are referring you can find the package, specifically under: Teaching&Training – MIPSfpga – English – MIPSfpga Labs v2.0. Given your teaching goals, maybe you will also find useful the third package of MIPSfpga, called MIPSfpga SoC.
The paper entitled “MIPSfpga: using a commercial MIPS soft-core in computer architecture education” describes in detail the 3 packages of MIPSfpga: (1) MIPSfpga GSG; (2) MIPSfpga Labs; and (3) MIPSfpga SoC. If you cannot access the paper, please give me your e-mail and I’ll send it to you.
Please let me know if you need more help.