- December 9, 2015 at 11:13 am #52202
Since nexys 3 only has 72KB block RAM.
Is it possible to use LUT for memory instead of using block RAM?
LeiDecember 18, 2015 at 7:14 am #52263
The block memory needed in MIPSfpga Getting Started and Fundamentals for program memory can be big or small depending on the amount of program code you need to load.
Two major point to note is that there is a Spartan 6 on Nexys3
Spartan 6 cannot be used with Vivado and you will have to use ISE. All projects in MIPSfpga are based on Vivado. So the back-port to ISE would be manual.
And it might not fit the complete logic required for MIPSfpga in the available logic blocks. Please synthesize a MIPSfpga vivado project and check resource utilization to see if it is possible to fit on the spartan 6 part.
For MIPSfpga SoC, I would highly recommend upgrading to the Nexys4DDR board.
ZubairLKDecember 18, 2015 at 3:22 pm #52271
Thank you for your reply.
What is the minimum size of block memory for boot code?
LeiDecember 28, 2015 at 11:58 pm #52486
There is a version of boot code for MIPSfpga that fits just 1 kilobyte.
You can get it here – https://github.com/MIPSfpga/mipsfpga-plus/blob/master/programs/01_light_sensor/boot.S
The major difference between the version of boot code in MIPSfpga Getting Started Guide and this small version is that small version does not link to C startup code of ANSI C library crt0 – https://en.wikipedia.org/wiki/Crt0
If you are trying to fit MIPSfpga into Nexys 3 Spartan-6, I would recommend to remove some blocks, like EJTAG. You can still load the memory using UART as demonstrated in https://github.com/MIPSfpga/mipsfpga-plus
The difference between a regular MIPSfpga Getting Started Guide package and the improved package is illustrated below:
The original MIPSfpga Getting Started Guide package is similar to this:
MIPSfpga+ / mipsfpga-plus / MFP is a cleaned-up and improved variant of MIPSfpga-based system defined in MIPSfpga Getting Started (MFGS) package. The new features include:
1. The ability to load a software program using ubiquitous $5 FTDI-based USB-to-UART connector instead of $50 Bus Blaster that is difficult to get in some places of the globe
2. The ability to change the clock frequency on the fly from 50 or 25 MHz down to 1 Hz (one cycle a second) to observe the work of CPU in real time, including cache misses and pipeline forwarding
3. An example of integration of a light sensor with SPI protocol
4. Smaller software initialization sequence that fits in 1 KB instead of 8 KB memory, which allows porting MIPSfpga to a wider selection of FPGA boards, without using external memory
5. Miscellaneous fixes like improving AHB-Lite slave to handle narrow uncached writes of 1 or 2-byte sizes