Porting MIPSfpga to Terasic DE0-Nano board with Altera Cyclone IV FPGA

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    Andrea
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    MIPSfpga successfully synthesized using the Quartus Prime 15.1 for the Cyclone IV FPGA.
    Below the summary report.

    +———————————————————————————-+
    ; Flow Summary ;
    +————————————+———————————————+
    ; Flow Status ; Successful – Tue Feb 16 21:23:50 2016 ;
    ; Quartus Prime Version ; 15.1.0 Build 185 10/21/2015 SJ Lite Edition ;
    ; Revision Name ; de0_nano ;
    ; Top-level Entity Name ; de0_nano ;
    ; Family ; Cyclone IV E ;
    ; Device ; EP4CE22F17C6 ;
    ; Timing Models ; Final ;
    ; Total logic elements ; 15,392 / 22,320 ( 69 % ) ;
    ; Total combinational functions ; 13,879 / 22,320 ( 62 % ) ;
    ; Dedicated logic registers ; 7,638 / 22,320 ( 34 % ) ;
    ; Total registers ; 7638 ;
    ; Total pins ; 154 / 154 ( 100 % ) ;
    ; Total virtual pins ; 0 ;
    ; Total memory bits ; 143,744 / 608,256 ( 24 % ) ;
    ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
    ; Total PLLs ; 0 / 4 ( 0 % ) ;
    +————————————+———————————————+

    Correctly generated the bitstream file de0_nano.sof and downloaded on DE0-Nano without errors.
    It works properly!

    The files are available on https://github.com/MIPSfpga/mipsfpga-plus

    1 user thanked author for this post.
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