PVRTC vs ETC2/EAC on Series 6 PowerVR GPUs

This topic contains 4 replies, has 3 voices, and was last updated by  Joe Davis 1 year, 5 months ago.

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  • #53707

    To find out which texture formats to use in my next mobile game I performed raw texturing tests with the latest PowerVR GPUs (series 6).

    I came to the conclusion that the support of ETC2/EAC textures (required in OpenGL ES 3.x) is somehow limited 🙁

    PVRTC textures perform much better. I tested only 4bit vs 4bit per pixel formats. Could it be that ETC2 textures are uncompressed in the GPUs texture caches or have other limitations along the way?

    Best,
    Chris

    #53748

    Simon
    Moderator

    Is there a full alpha channel in your textures? If so I believe ETC2 will become GL_COMPRESSED_RGBA8_ETC2_EAC and thus becomes 8bpp rather than 4bpp. (see https://www.khronos.org/opengles/sdk/docs/man3/html/glCompressedTexImage2D.xhtml )

    PVRTC will remain at 4bpp (though that can imply a lower quality as it may be attempting to pack more data into the same space)

    1 user thanked author for this post.
    #53750

    Hi Simon,

    I’ve only tested 4bit ETC (GL_ETC1_RGB8_OES) vs 4bit PVRTC (GL_COMPRESSED_RGB_PVRTC_4BPPV1_IMG) without alpha so far. Sorry for the confusion.

    Performance wise they should be equal (only speed not quality)?

    Best,
    Chris

    #53752

    Simon
    Moderator

    No need to apologise 😀

    I’ve only tested 4bit ETC (GL_ETC1_RGB8_OES) vs 4bit PVRTC (GL_COMPRESSED_RGB_PVRTC_4BPPV1_IMG) without alpha so far.

    Performance wise they should be equal (only speed not quality)?

    In that case I would think performance should be the same. Although I’m more familiar with the PVRTC HW, to my knowledge, both should deliver the same rate of decompressed texels to the texture unit and consume approximately the same external bandwidth.

    @Joe : Would I be right in assuming the memory layout for ETC* is in either a Morton-like or Tiled order?

    #53763

    Joe Davis
    Member

    @Joe : Would I be right in assuming the memory layout for ETC* is in either a Morton-like or Tiled order?

    I suspect it’s up to the driver to optimize the memory layout during upload, but I’d need to check.

    Can you share your ETC vs. PVRTC benchmark with us to investigate the performance delta?

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