Why there is a tick before instance?

This topic contains 1 reply, has 2 voices, and was last updated by  Kirill 1 year, 7 months ago.

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  • #53039

    Lei
    Member

    Hi,

    The file m14k_edp.v, Iine 1130 has the following code:

    `M14K_EDP_ADD edp_add( .a(aop_e),
    .b(bop_e),
    .ci(mpc_subtract_e),
    .s(adder_res_e),

    .co(car31_e),
    .c31(c31_e));

    I am new to Verilog, could anyone tell me why there is a tick before instantiation?

    Best wishes,
    Lei

    #53217

    Kirill
    Member

    {I am new to Verilog, could anyone tell me why there is a tick before instantiation?}

    `M14K_EDP_ADD is a define which is described in m14k_config.vh.

    2 users thanked author for this post.
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