MIPSfpga One-Day Workshops in Germany

12 Jan 2017
Novotel Munich Airport, Munich


Hands-on with a MIPS core for teaching & projects!

 “Teaching Computer Architecture using MIPSfpga and the
Digilent Nexys 4 DDR platform with a Xilinx Artix 7 FPGA”

 

img-xilinx-digilent

 

The Imagination University Programme is pleased to host a workshop specifically for teachers, based on the award winning “MIPSfpga” core. MIPSfpga is the RTL source code of the MIPS microAptiv for implementation on an FPGA. It is a member of the same family found in many embedded devices, including the popular PIC32MZ microcontroller from Microchip, Mediatek/SEEED Studio’s new LinkItSmart7688 and Samsung’s Artik1.

This workshop will show you how to use this core as part of a Computer Architecture course, which will pave the way for your students to use it in their projects, in effect creating their own SoC designs. MIPSfpga is the real “industrial” RTL, non-obfuscated, and available freely for academic use. These workshops are part of a global programme of events to enable teachers to harness this wonderful technology. You can be among the first to get hands-on with MIPSfpga!


Location & Date: The Novotel, Munich Airport. Thursday January 12th 2017

Agenda           The workshop starts at 09:30 and ends by 18:00.

  • Welcome
  • Introduction to MIPSfpga
  • MIPSfpga and Vivado Demonstration:
    • Simulation: Increment LEDs program
    • Increment LEDs delay program on the Nexys 4 DDR
    • Synthesizing core on the Nexys4 DDR
    • Codescape MIPS SDK: using Codescape to develop & debug C and assembly code
    • Bus Blaster/OpenOCD: using the Bus Blaster JTAG probe and OpenOCD to debug a target system
  • Lab 1: Writing C code
  • Lab 2: Adding a 7-segment display I/O
  • Integrating Xilinx IP blocks with MIPSfpga
  • Porting to other boards – Example: Digilent’s Basys3
  • Teaching Materials for MIPSfpga / Q&A
  • Introduction to the Imagination University Programme (IUP)

After your day of training you will be proficient in porting MIPSfpga to a suitable platform, and aware of its potential to revolutionise your teaching of Computer Architecture.
All delegates will be given access to:

  • MIPSfpga core
  • The full Getting Started Guide (written by Prof. Sarah Harris, co-author of Digital Design & Computer Architecture by Harris & Harris, with contributions from Xilinx)
  • Detailed reference documentation about MIPS microAptiv.
  • Other vital information/programs that enable the whole package to work effectively.

Trainers

  • Professor Daniel Chaver-Martinez University de Complutense, Madrid
  • Itai Yarom Solutions Engineering at Imagination Technologies
  • Sean Raby Solutions Engineering at Imagination Technologies
  • Robert Owen Manager Imagination University Programme

Eligibility

  • Free of charge for members of academia.
  • Open to academic faculty members, with a priority for those involved directly in teaching.
  • The workshop will be given in English
  • Prior experiences of Vivado or Codescape MIPS SDK are useful but not essential.
  • If over-booked, we reserve the right to accept or refuse registrations based on our desire to enable the widest number of universities and colleges to participate

Registration   Please apply online here


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