MIPSfpga One-Day Workshops in India

23 May - 27 May 2016
Pune, Hyderbad


Get Hands-on With A Non-obfuscated Fully-verified MIPS Core for Teaching and Projects!

 “Teaching Computer Architecture using MIPSfpga and the
Digilent Nexys 4 DDR platform with a Xilinx Artix 7 FPGA”

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Imagination University Programme is pleased to host a series of workshops specifically for teachers, based on the award winning “MIPSfpga” Core. MIPSfpga is the RTL source code of the MIPS microAptiv for implementation on an FPGA. It is a member of the same family found in many embedded devices, including the popular PIC32MZ microcontroller from Microchip and Samsung’s new Artik1.

This workshop will show you how to use this core as part of a Computer Architecture course, which will pave the way for your students to use it in their projects, in effect creating their own SoC designs.

With its long heritage and excellent documentation MIPS is the preferred choice of RISC architecture for many teachers around the world. In the past, teachers had to settle for creating partial “MIPS-like” cores or using unofficial copies of dubious heritage to demonstrate key concepts. Not now! MIPSfpga is the real “industrial” RTL, non-obfuscated, and available freely for academic use.

These workshops are part of a global programme of events to enable teachers to harness this wonderful technology. You can be among the first to get hands-on with MIPSfpga!


Workshop Details

Locations/Date
College of Engineering, Pune on 23rd or 24th May 2016
VEDA Institute of Information Technology Pvt. Ltd., Hyderabad: 26th or 27th May 2016

Agenda

It starts at 09:30 and ends at 18:00.

  • Welcome & Introduction to the Imagination University Programme (IUP)
  • Introduction to MIPSfpga
  • MIPSfpga and Vivado Demonstration:
    • Simulation: Increment LEDs program
    • Increment LEDs delay program on the Nexys 4 DDR
    • Synthesizing core on the Nexys4 DDR
    • Codescape MIPS SDK: using Codescape to develop & debug C and assembly code
    • Bus Blaster/OpenOCD: using the Bus Blaster JTAG probe and OpenOCD to debug a target system
  • Lab 1: Writing C code
  • Lab 2: Adding a 7-segment display I/O
  • Integrating Xilinx IP blocks with MIPSfpga
  • Porting to other boards – Example: Digilent’s Basys3
  • Teaching Materials for MIPSfpga / Wrap-up / Q&A

After your day of training you will be proficient in porting MIPSfpga to a suitable platform, and aware of its potential to revolutionise your teaching of Computer Architecture.
All delegates will be given access instructions to the
– MIPSfpga core.
– The full Getting Started Guide (written by Sarah Harris with contributions from Xilinx).
– Detailed reference documentation about MIPS microAptiv.
– Other vital information/programs that enable the whole package to work effectively.

Trainers
Preparation

You are recommended to use the pre-configured workstations provided at the venue

Eligibility

These workshops are free of charge for members of academia but places are limited and demand will be strong, so please apply for your place quickly. Please do not apply if you are not sure you can attend.

  • Free of charge for members of academia.
  • These workshops are open to academic faculty members, with a priority for those involved directly in teaching.
  • We reserve the right to accept or refuse registrations based on our desire to enable the broadest spectrum of universities and colleges to participate.
  • Prior experience of Vivado or Codescape MIPS SDK are useful but not essential.

 

Registration

Please apply online here.


Find out about the Imagination University Programme

For more information or enquiries, please visit our University Programme Page or IUP Forum.The IUP Team will be on-hand to discuss your interests. To stay in touch, please register for the Imagination University Programme here

You are invited to please circulate this workshop to academic friends and colleagues…


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